In wireline communication systems, a data signal received at a receiving circuit may have a low voltage potential or a high voltage potential to represent a binary value of zero or one, respectively. A portion of the data signal is transmitted for a duration of time, also known as a bit time. The bit time represents the time during which a single binary value is transmitted. The bit time is inversely proportional to the frequency of the data signal transmission.
The data signal transmission for a bit time has a portion of time in which the binary value is represented by a valid voltage potential. The remaining portion of time is needed for transitions from one voltage potential to another. The portion of time that the binary value is valid is referred to as a data eye.
To increase processor performance, clock frequencies used by microprocessors, often referred to as “CPUs,” have increased. Also, as the number of circuits that can be used in a CPU has increased, the number of parallel operations has risen. As processor performance continues to increase, the result has been a larger number of circuits switching at faster rates. Thus, from a design perspective, important considerations, such as switching noise and signal integrity must be taken into account. Signals may have undesirable switching characteristics caused by noise.
As the frequencies of modem computers continue to increase, the need to rapidly transmit data between chip interfaces also increases. To accurately receive the data signal, a clock is often sent to help recover the data signal (also known as source synchronous transmission). The clock determines when the data signal should be latched by a receiver's circuits. As the frequency of the data signal transmission increases, the bit time decreases. Accordingly, the data eye becomes narrower.
FIG. 1 shows a block diagram of a typical computer system component (10). The computer system (10) includes a link, where the link may include data lines and an associated clock line. Data lines (14) that are N bits wide connect between circuit A (12) and circuit B (34). To aid in the recovery of a transmitted data signal on the data lines (14), a clock signal on the clock line (16) is transmitted with the data signal to determine when the data signal should be latched. Multiple links may connect between circuit A (12) and circuit B (34).
The data signal on the data lines (14) are transmitted from circuit A (12) to circuit B (34). Circuit A (12) and circuit B (34) could also have one or more links to transmit data from circuit B (34) to circuit A (12) including one or more additional clock signals (not shown). Alternatively, the links between circuit A (12) and circuit B (34) could be bi-directional. The decision as to which circuit may transmit at any given time is defined by a protocol.
FIG. 2 shows a block diagram of a communication system (200). A data signal (201) is transmitted by an output buffer (202). A transmitting circuit (208) includes the output buffer (202), and generates, or receives, the data signal (201). The transmitted data signal is output onto a data line (214). The transmitted data signal on data line (214) may attenuate during transmission from the transmitting circuit (208) to a receiving circuit (210). An input buffer (204) included in the receiving circuit (210) recovers and regenerates the transmitted data signal to valid voltage potentials.
In FIG. 2, a recovered data signal (220) is input to a latch (206). The latch (206) outputs a copy of the recovered data signal (220) as a latched data signal (222) when a clock signal (224) transitions from a low voltage potential to a high voltage potential. The clock signal (224) is responsive to a clock signal generated by the transmitting circuit (208). The clock signal (224) may be connected directly to the transmitting circuit (208). The clock signal (224) may incur a phase shift as a result of additional circuitry (not shown) included in the receiving circuit (210). The additional circuitry (not shown) may be directly connected to the clock signal generated by the transmitting circuit (208).
FIG. 3 shows a timing diagram (300). A data signal (301) is recovered after transmission across a data line. The data signal (301) is input to a latch, for example, latch (206) in FIG. 2. Clock signal (303) causes the data signal (301) to be latched on a low voltage potential to high voltage potential transition of the clock signal (303).
One common signal performance issue is jitter. Jitter is the time domain error from poor spectral purity of a signal. In a repeated signal pattern, such as a clock signal, a transition that occurs from one state to another that does not happen at the same time relative to other transitions is said to have jitter. Jitter represents the perturbations that result in the intermittent shortening or lengthening of signal elements.
In FIG. 3, the clock signal (303) may jitter. The clock signal (303) is shown with added jitter (305). In this example, the clock signal with jitter (305) has enough jitter that the clock transition from a low voltage potential to a high voltage potential does not occur during the bit time. In other words, the clock signal with jitter (305) transitions outside of the data eye.
To properly latch a data signal, the data eye must be wider than the jitter in the clock signal. Jitter in the clock signal limits the frequency of a data signal transmission. One approach has been to use external inductors to help regulate clock generation. However, adding inductors increases a communication system's cost.